The integration of typical two-dimensional or planar semiconductor devices may be mainly determined by the area occupied by a unit memory cell and may be influenced by the level of a fine pattern forming technology. However, the expensive processing equipment that may be needed to increase pattern fineness may set a practical limitation on the increase in the level of integration for two-dimensional or planar semiconductor devices. To overcome such a limitation, there have been recently proposed three-dimensional semiconductor memory devices including three-dimensionally arranged memory cells.